Long time no see. My website has been down for a while (technical issues - web experts contact me if you want to help) but now it's up again. And going through some of my old articles here (well, they're all old, I should probably do something about it...) I came across an interview I did some 4 years ago with Mark Hampton, co-founder of Certess - the company that developed Certitude. For those who don't know - Certitude is a cool technology that verifies that your verification environment really does its job. I thought their technology was really exciting and could see how it might change the way verifiers thought about "verification closure".
Anyway, 4 years have passed and today I work at Synopsys who back in 2012 acquired this technology (through SpringSoft) . I can run Cerittude on my laptop and then go to lunch with a Certitude expert. That's what I call closure!
I will make an effort to continue blogging, but I will need your help to keep me motivated. You can start by leaving a comment to share your thoughts on verification.
A couple of years ago I wrote here about how the UVM was becoming the next big thing in the verification world.
And guess what? I was right. Not that it was too hard to predict... but anyway, the industry has finally standardized on language (SV) and methodology (UVM) which is great news for us verification folks. The bad news is that even with SystemVerilog and UVM becoming ubiquitious, still we have to spend a fair amount of our time debugging our DUTs. And this is where the tools can be of much help.
SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get familiar with SystemVerilog unless you want to stay in the dark.