Articles Think Verification - Tips & Insights on ASIC Verification - trends, insights, tutorials, videos, tips, and lots of cool stuff Sun, 17 Feb 2019 03:12:25 +0000 Joomla! 1.5 - Open Source Content Management en-gb Cool Things You Can Do with Verdi Wow it's been a while, but I'm back with a new series of YouTube videos. Hurray !!

This time it's all about Verdi and all the cool things it can do for you.

Since most of you guys already know it is the best debugger out there, my goal is to show you other aspects of Verdi, primarily Coverage and Verification Planinng.

If you don't know what I'm talking about - you should definitely check this video out.


]]> (Administrator) Main Tue, 22 Jul 2014 15:32:07 +0000
My Story With Certitude Long time no see. My website has been down for a while (technical issues - web experts contact me if you want to help) but now it's up again. And going through some of my old articles here (well, they're all old, I should probably do something about it...) I came across an interview I did some 4 years ago with Mark Hampton, co-founder of Certess - the company that developed Certitude. For those who don't know - Certitude is a cool technology that verifies that your verification environment really does its job. I thought their technology was really exciting and could see how it might change the way verifiers thought about "verification closure".

Anyway, 4 years have passed and today I work at Synopsys who back in 2012 acquired this technology (through SpringSoft) . I can run Cerittude on my laptop and then go to lunch with a Certitude expert. That's what I call closure! 

I will make an effort to continue blogging, but I will need your help to keep me motivated. You can start by leaving a comment to share your thoughts on verification.


Oh - and if you want to catch up with Certitude - here's a great place to start.

]]> (Administrator) Main Fri, 26 Jul 2013 08:01:45 +0000
UVM Users: Here Are Some Great Tips [Video] A couple of years ago I wrote here about how the UVM was becoming the next big thing in the verification world.

And guess what? I was right. Not that it was too hard to predict... but anyway, the industry has finally standardized on language (SV) and methodology (UVM) which is great news for us verification folks. The bad news is that even with SystemVerilog and UVM becoming ubiquitious, still we have to spend a fair amount of our time debugging our DUTs. And this is where the tools can be of much help.


]]> (Administrator) Main Fri, 15 Jun 2012 20:35:44 +0000
Let The New Game Begin Things are changing. The EDA industry is changing, and the verification world is changing (check out Janick Bergeron's inspiring talk at SNUG San Jose for a glimpse of the future of verification). One of the major challenges we’re already facing today is an increasing number of IP blocks in a single system. Designs are getting bigger and bigger, and the focus is shifting towards system level integration rather than “design creation”.

]]> (Administrator) Main Mon, 07 Jun 2010 14:02:12 +0000
Eternal Sunshine of the Verifier's Mind To be successful in verification you not only need to possess the right technical skills, but you also need to possess the right mindset. Possessing the right mindset will lead you to success rapidly. Here are 3 things that I’ve found very important to keep in mind with everything you do in verification:

]]> (Administrator) Main Wed, 03 Mar 2010 16:39:12 +0000
About UVM And You There’s been a lot of buzz about the UVM lately and for a reason. The Universal Verification Methodology is about to change the rules of the game pretty soon, if not already. That is interesting because not too long ago verification engineers questioned the need for adopting any verification methodology… Today, however, the question is entirely different – it is WHICH methodology to adopt. So as the UVM is gradually taking form and drawing the attention of verification stakeholders I think it’s a great time to stop and remind ourselves why we need a verification methodology in the first place, and more importantly - what makes a verification methodology so good that the only question about it would be “how quickly can I learn it”?  I have identified 3 elements of a good verification methodology that work together, each on a separate track, to make it do its magic. The first element is Guidance, the second is Efficiency, and the third one – perhaps the most exciting one – is what I call The Real Added Value.

]]> (Administrator) Main Mon, 01 Mar 2010 16:52:01 +0000
Who Wants To Be A Verifier? Are you looking for a job in verification? Are you pursuing a career in verification? Congratulations! There a few things you might want to consider about your prospective employer before you sign the contract. In today's important article we'll try to analyze semiconductor companies using a two dimensional framework. If you find enough information about your potential employers in advance, you'll be able to position them correctly on both axes thus helping you make a better decision regarding your future career.

]]> (Administrator) Main Thu, 14 Jan 2010 21:49:38 +0000
To Do List 2010 Introducing Philip Americus - a new guest blogger here on Think Verification. Phil is an ASIC veteran who's worked with every phase of ASIC design - from initial concept to tapeout, with an emphasis on verification, including management of both HW and SW engineers. This is his debut post on our website:

When I first started my Engineering career we had Verilog-95 and VHDL.  Combine this with some wrappers, in C, Perl, or Csh, and we accomplished Verification just fine.  As designs became larger and more complex, we continually felt a need to go to higher level programming models.  In came Specman, SystemVerilog (Superlog!), SystemC, model checking, etc. to meet the challenge. Some companies embraced these new technologies and some stuck with the old.  ]]> (Administrator) Main Sun, 03 Jan 2010 12:37:08 +0000
The Big Picture
Great verification engineers know the secret - if they want to be successful they must also understand the essence of the entire chip design flow, from concept to working samples. Here are some great videos that will help you see the big picture a bit better. ]]> (Administrator) Main Thu, 24 Dec 2009 17:15:50 +0000 Inside The Verifiers Cubicle Have you ever watched Inside the Actors Studio? You know, the show where James Lipton hosts famous actors in front of a small audience of students? Remember?
Anyway, this is actually one of my favorite shows on TV (and there aren’t that many really). Towards the end of each show Lipton usually does the Bernard Pivot questionnaire “ he asks the celebrity a series of short questions such as what is your favorite word / curse word / sound and it’s really interesting and funny to hear the answers. I even learned that Natalie Portman and I have one thing in common “ our favorite curse word...

]]> (Administrator) Main Thu, 24 Dec 2009 17:14:01 +0000