Specman Compiled Mode Print
User Rating: / 8
Thursday, 24 December 2009 15:18

This is a really short tutorial that demonstrates the entire process of compiling and running a simulation with NC-Verilog & Specman (using compiled specman).


Consider the following sample design - my_xor.v:

module my_xor (A,B,Y);
    input A;
    input B;
    output Y;
    assign Y = A ^ B;

A very complex DUT as you may have noticed.

Now let’s add the environment - env.e:

extend sys {
   run() is also {
        start my_test();
    my_test()@sys.any is {
       out( ==== START ,sys.time);
       wait delay (1000 ns);
       ’~/my_xor/A’ = 1;
       ’~/my_xor/B’ = 0;
       wait delay (1000 ns);
       ’~/my_xor/A’ = 0;
       wait delay (1000 ns);
       out( ==== END ,sys.time);

It’s a just a quick demo env so excuse the coding style. And now for the fun part - Let’s simulate our little environment with the DUT - 
Open a fresh terminal and make sure you got the 2 files at your current dir (copy & paste into my_xor.v and env.e) and follow these steps:

1. First , compile the e code into a shared library so that an executable file is created and also a corresponding esv file:
%sn_compile.sh -shlib -exe env.e

2. Use the newly created executable file (env) to create verilog stubs file:
%./env -c write stubs -ncvlog

3. Compile the verilog code plus the newly created stub file (specman.v):
%ncvlog -MESSAGES -UPDATE my_xor.v specman.v

4.  Elaborate the design:
%ncelab_specman specman my_xor -snapshot my_xor -access +rwc

5. Now you have to tell Specman where to find the compilation results
%setenv SPECMAN_DLIB ./libsn_env.so

6. That’s is - now run the simulation:
%specrun -p test ncsim -nbasync my_xor

As usual, read the manual to get the full picture but the example above should give you the hang of it and may be used as reference. And if you were wondering if there was a single script solution for this, well - there is. Cadence recently released the irun script which should take care of everything you always wanted from your simulator but were afraid to ask. Quite a catchy name for a script, don’t you think?


More articles :

» Educate Yourself - SystemVerilog 101

SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get...

» Let The New Game Begin

Things are changing. The EDA industry is changing, and the verification world is changing (check out Janick Bergeron's inspiring at SNUG San Jose for a glimpse of the future of verification). One of the major challenges we’re already facing today...

» The Cost Of Verification

We spend about one third of our lives in bed, right? doesn’t it make sense then to buy a good bed and not a cheap one? The same can be said for your verification tools as you spend so much of your project time on verification. Buying cheaper tools...

» My Story With Certitude

Long time no see. My website has been down for a while (technical issues - web experts contact me if you want to help) but now it's up again. And going through some of my old articles here (well, they're all old, I should probably do something about...

» VMM Hackers Guide - Default Behavior For Your BFM

Here's a short tutorial on how to implement a default behavior for your BFM using VMM. Some protocols require constant activity on their interface even when you don't have any data to transmit. This means you must have a mechanism that drives idle...