Tutorials Think Verification - Tips & Insights on ASIC Verification - trends, insights, tutorials, videos, tips, and lots of cool stuff http://thinkverification.com/index.php?option=com_content&view=section&id=5&layout=blog&Itemid=7 Thu, 18 Apr 2019 12:48:23 +0000 Joomla! 1.5 - Open Source Content Management en-gb Using Constrained-Random Verification with Legacy Testbenches http://thinkverification.com/index.php?option=com_content&view=article&id=56:using-constrained-random-verification-with-legacy-testbenches&catid=6:systemverilog&Itemid=13 http://thinkverification.com/index.php?option=com_content&view=article&id=56:using-constrained-random-verification-with-legacy-testbenches&catid=6:systemverilog&Itemid=13 One of SystemVerilog's noticeable features is that it is basically a "design language" that has been extended with verification capabilities. This might be an advantage or not, depending on who you're asking, but obviously, if you only want to use a limited number of verification capabilities to gradually extend your existing Verilog testbench, SystemVerilog might be a good solution. This is a bottom-up approach where you want to retain your old verilog code (typically transactors) and add stuff like randomization and maybe coverage on top. Think Verification recommends, though, that you seriously consider a top-down approach as well (read: lose your old testbench), because a top-down approach provides a comprehensive solution to the verification problem. But today we're going to talk about the former approach which is a more pragmatic one in certain cases and we have a special guest for that.

admin@thinkverification.com (Administrator) SystemVerilog Tue, 23 Mar 2010 12:08:20 +0000
Educate Yourself - SystemVerilog 101 http://thinkverification.com/index.php?option=com_content&view=article&id=49:educate-yourself-systemverilog-101&catid=6:systemverilog&Itemid=13 http://thinkverification.com/index.php?option=com_content&view=article&id=49:educate-yourself-systemverilog-101&catid=6:systemverilog&Itemid=13 SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get familiar with SystemVerilog unless you want to stay in the dark.

admin@thinkverification.com (Administrator) SystemVerilog Sun, 03 Jan 2010 14:22:56 +0000
VMM Hackers Guide - Creating Smart Scenarios With Atomic Generators http://thinkverification.com/index.php?option=com_content&view=article&id=34:vmm-hackers-guide-creating-smart-scenarios-with-atomic-generators&catid=6:systemverilog&Itemid=13 http://thinkverification.com/index.php?option=com_content&view=article&id=34:vmm-hackers-guide-creating-smart-scenarios-with-atomic-generators&catid=6:systemverilog&Itemid=13 VMM ships with some pretty useful built-in components and applications. VMM''s Atomic Generator is probably one of the most powerful ones, yet it's pretty basic. It can definitely help you generate a flow of random items but it was not intended for generation of sequences. A sequence (a.k.a scenario) is a set of items that have some sort of correlation between them. For example - a set of 10 transactions with incremental addresses, or a set of 3 packets where the first one is always short and the last one is always long.

admin@thinkverification.com (Administrator) SystemVerilog Thu, 24 Dec 2009 16:59:09 +0000
VMM Hackers Guide - Default Behavior For Your BFM http://thinkverification.com/index.php?option=com_content&view=article&id=33:vmm-hackers-guide-default-behavior-for-your-bfm&catid=6:systemverilog&Itemid=13 http://thinkverification.com/index.php?option=com_content&view=article&id=33:vmm-hackers-guide-default-behavior-for-your-bfm&catid=6:systemverilog&Itemid=13 Here's a short tutorial on how to implement a default behavior for your BFM using VMM.
Some protocols require constant activity on their interface even when you don't have any data to transmit. This means you must have a mechanism that drives idle packets or dummy data items as long as the generator doesn't produce items for its BFM. In VMM, Generators are connected to BFMs using vmm_channels and we''re just about to show you how to take advantage of that for our needs. ]]>
admin@thinkverification.com (Administrator) SystemVerilog Thu, 24 Dec 2009 16:58:37 +0000
VMM Hackers Guide - Shutting Down Atomic Generators http://thinkverification.com/index.php?option=com_content&view=article&id=32:vmm-hackers-guide-shutting-down-atomic-generators&catid=6:systemverilog&Itemid=13 http://thinkverification.com/index.php?option=com_content&view=article&id=32:vmm-hackers-guide-shutting-down-atomic-generators&catid=6:systemverilog&Itemid=13 Everybody likes atomic generators. If you have a vmm_data class, all you have to do is add a quick macro line and you get a free VMM-compliant generator that you only need to instantiate in your environment. An atomic generator is a simple yet powerful means to create a continuous flow of random data items to your DUT (more accurately “ to your BFM). Once everything is hooked up, all you have to do in your test program is set the number of items you want to generate, or let it run endlessly.

admin@thinkverification.com (Administrator) SystemVerilog Thu, 24 Dec 2009 16:57:59 +0000
Smart Constraints In SystemVerilog http://thinkverification.com/index.php?option=com_content&view=article&id=31:tutorial-smart-constraints-in-systemverilog&catid=6:systemverilog&Itemid=13 http://thinkverification.com/index.php?option=com_content&view=article&id=31:tutorial-smart-constraints-in-systemverilog&catid=6:systemverilog&Itemid=13 Constraints are our best friends when it comes to random generation. They allow us to limit the range of possible scenarios/values as much as we like, from the level of "everything is allowed" down to the level of such heavy constraints that really imply a very directed scenario. In most cases what we want to is to have a set of default constraints that give us a nice distribution of scenarios and values. We will then need to override the default set in some of our test cases by applying additional constraints, or reshaping the distribution or even removing previous constraints. Here's a cool way to do this in SystemVerilog:

admin@thinkverification.com (Administrator) SystemVerilog Thu, 24 Dec 2009 16:55:32 +0000
Method Manipulation In SV and e http://thinkverification.com/index.php?option=com_content&view=article&id=27:tutorial-method-manipulation-in-sv-and-e&catid=6:systemverilog&Itemid=13 http://thinkverification.com/index.php?option=com_content&view=article&id=27:tutorial-method-manipulation-in-sv-and-e&catid=6:systemverilog&Itemid=13 If you're familiar with SystemVerilog and taking your first steps in e (or vice versa) you might find this useful. Here are some of the most common method manipulations that you''ll need to master and how you should go about implementing them in e and SV:

admin@thinkverification.com (Administrator) SystemVerilog Thu, 24 Dec 2009 16:46:54 +0000
Useful OVM-e Snippets http://thinkverification.com/index.php?option=com_content&view=article&id=24:tutorial-useful-ovm-e-snippets&catid=7:specman-e&Itemid=12 http://thinkverification.com/index.php?option=com_content&view=article&id=24:tutorial-useful-ovm-e-snippets&catid=7:specman-e&Itemid=12 How to activate Specman Profiler? How to get rid of automatic vr_ad coverage? Let's find out.

admin@thinkverification.com (Administrator) Specman-e Thu, 24 Dec 2009 16:41:29 +0000
Packing In OVM-e http://thinkverification.com/index.php?option=com_content&view=article&id=23:tutorial-packing-in-ovm-e&catid=7:specman-e&Itemid=12 http://thinkverification.com/index.php?option=com_content&view=article&id=23:tutorial-packing-in-ovm-e&catid=7:specman-e&Itemid=12 This example shows how to pack a struct into a list of Double Words (32 bit) keeping the original order. This time we got less talking, and more code:

admin@thinkverification.com (Administrator) Specman-e Thu, 24 Dec 2009 16:40:46 +0000
How To Validate Type-Casting In OVM-e http://thinkverification.com/index.php?option=com_content&view=article&id=21:tutorial-how-to-validate-type-casting-in-ovm-e&catid=7:specman-e&Itemid=12 http://thinkverification.com/index.php?option=com_content&view=article&id=21:tutorial-how-to-validate-type-casting-in-ovm-e&catid=7:specman-e&Itemid=12 Before type-casting an e variable ("as_a"), we often want to check the validity of the operation (this is quite similar in concept to $cast in SystenVerilog). The reason is simple, in case the casting operation failed we would end up with a fatal error at run-time that otherwise could have been avoided. But how?

admin@thinkverification.com (Administrator) Specman-e Thu, 24 Dec 2009 16:37:51 +0000