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Using Constrained-Random Verification with Legacy Testbenches PDF Print E-mail
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Tuesday, 23 March 2010 12:08

One of SystemVerilog's noticeable features is that it is basically a "design language" that has been extended with verification capabilities. This might be an advantage or not, depending on who you're asking, but obviously, if you only want to use a limited number of verification capabilities to gradually extend your existing Verilog testbench, SystemVerilog might be a good solution. This is a bottom-up approach where you want to retain your old verilog code (typically transactors) and add stuff like randomization and maybe coverage on top. Think Verification recommends, though, that you seriously consider a top-down approach as well (read: lose your old testbench), because a top-down approach provides a comprehensive solution to the verification problem. But today we're going to talk about the former approach which is a more pragmatic one in certain cases and we have a special guest for that.

 
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