Long time no see. My website has been down for a while (technical issues - web experts contact me if you want to help) but now it's up again. And going through some of my old articles here (well, they're all old, I should probably do something about it...) I came across an interview I did some 4 years ago with Mark Hampton, co-founder of Certess - the company that developed Certitude. For those who don't know - Certitude is a cool technology that verifies that your verification environment really does its job. I thought their technology was really exciting and could see how it might change the way verifiers thought about "verification closure".
Anyway, 4 years have passed and today I work at Synopsys who back in 2012 acquired this technology (through SpringSoft) . I can run Cerittude on my laptop and then go to lunch with a Certitude expert. That's what I call closure!
I will make an effort to continue blogging, but I will need your help to keep me motivated. You can start by leaving a comment to share your thoughts on verification.
A couple of years ago I wrote here about how the UVM was becoming the next big thing in the verification world.
And guess what? I was right. Not that it was too hard to predict... but anyway, the industry has finally standardized on language (SV) and methodology (UVM) which is great news for us verification folks. The bad news is that even with SystemVerilog and UVM becoming ubiquitious, still we have to spend a fair amount of our time debugging our DUTs. And this is where the tools can be of much help.
Things are changing. The EDA industry is changing, and the verification world is changing (check out Janick Bergeron's inspiring talk at SNUG San Jose for a glimpse of the future of verification). One of the major challenges we’re already facing today is an increasing number of IP blocks in a single system. Designs are getting bigger and bigger, and the focus is shifting towards system level integration rather than “design creation”.
Is Assertion-Based Verification (ABV) becoming mainstream? This question popped up today at Mentor’s ABV seminar. Assertions in general and ABV in particular make another approach that you can use to verify your design. Usually ABV alone is not sufficient, and is used alongside other verification approaches such as Coverage-Driven Verification, Directed Testing, Formal Verification, and Code Coverage. What’s good about ABV though, is that it’s the fastest tool around in terms of failure-to-root-cause time (also in your testbench!)