Home Articles

Search

Articles
About UVM And You PDF Print E-mail
User Rating: / 30
PoorBest 
Monday, 01 March 2010 16:52

There’s been a lot of buzz about the UVM lately and for a reason. The Universal Verification Methodology is about to change the rules of the game pretty soon, if not already. That is interesting because not too long ago verification engineers questioned the need for adopting any verification methodology… Today, however, the question is entirely different – it is WHICH methodology to adopt. So as the UVM is gradually taking form and drawing the attention of verification stakeholders I think it’s a great time to stop and remind ourselves why we need a verification methodology in the first place, and more importantly - what makes a verification methodology so good that the only question about it would be “how quickly can I learn it”?  I have identified 3 elements of a good verification methodology that work together, each on a separate track, to make it do its magic. The first element is Guidance, the second is Efficiency, and the third one – perhaps the most exciting one – is what I call The Real Added Value.

 
Who Wants To Be A Verifier? PDF Print E-mail
User Rating: / 22
PoorBest 
Thursday, 14 January 2010 21:49

Are you looking for a job in verification? Are you pursuing a career in verification? Congratulations! There a few things you might want to consider about your prospective employer before you sign the contract. In today's important article we'll try to analyze semiconductor companies using a two dimensional framework. If you find enough information about your potential employers in advance, you'll be able to position them correctly on both axes thus helping you make a better decision regarding your future career.

 
Prepare For Your Next Job Interview PDF Print E-mail
User Rating: / 25
PoorBest 
Wednesday, 06 January 2010 16:10

Succeeding at job interviews requires practice. If you're applying for a verification job you'd better get yourself well prepared both mentally and technically. Nevertheless, a great deal of tension could be avoided if you knew in advance what sort of technical questions you might be facing. Different managers will ask different questions, usually from their own area of expertise, and not necessarily yours. So, we've collected for you some of the best websites that offer job interview questions that should help you in your next verification job interview. Wouldn't hurt to review them and plan your answers in advance.

 
To Do List 2010 PDF Print E-mail
User Rating: / 4
PoorBest 
Sunday, 03 January 2010 12:37
Introducing Philip Americus - a new guest blogger here on Think Verification. Phil is an ASIC veteran who's worked with every phase of ASIC design - from initial concept to tapeout, with an emphasis on verification, including management of both HW and SW engineers. This is his debut post on our website:

When I first started my Engineering career we had Verilog-95 and VHDL.  Combine this with some wrappers, in C, Perl, or Csh, and we accomplished Verification just fine.  As designs became larger and more complex, we continually felt a need to go to higher level programming models.  In came Specman, SystemVerilog (Superlog!), SystemC, model checking, etc. to meet the challenge. Some companies embraced these new technologies and some stuck with the old. 
 
The Big Picture PDF Print E-mail
Thursday, 24 December 2009 17:15
Great verification engineers know the secret - if they want to be successful they must also understand the essence of the entire chip design flow, from concept to working samples. Here are some great videos that will help you see the big picture a bit better.
 
«StartPrev12345NextEnd»

Page 2 of 5
Copyright © 2017 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.