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Smart Constraints In SystemVerilog PDF Print E-mail
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Thursday, 24 December 2009 16:55

Constraints are our best friends when it comes to random generation. They allow us to limit the range of possible scenarios/values as much as we like, from the level of "everything is allowed" down to the level of such heavy constraints that really imply a very directed scenario. In most cases what we want to is to have a set of default constraints that give us a nice distribution of scenarios and values. We will then need to override the default set in some of our test cases by applying additional constraints, or reshaping the distribution or even removing previous constraints. Here's a cool way to do this in SystemVerilog:

 
Method Manipulation In SV and e PDF Print E-mail
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Thursday, 24 December 2009 16:46

If you're familiar with SystemVerilog and taking your first steps in e (or vice versa) you might find this useful. Here are some of the most common method manipulations that you''ll need to master and how you should go about implementing them in e and SV:

 
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