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Using Constrained-Random Verification with Legacy Testbenches PDF Print E-mail
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Tuesday, 23 March 2010 12:08

One of SystemVerilog's noticeable features is that it is basically a "design language" that has been extended with verification capabilities. This might be an advantage or not, depending on who you're asking, but obviously, if you only want to use a limited number of verification capabilities to gradually extend your existing Verilog testbench, SystemVerilog might be a good solution. This is a bottom-up approach where you want to retain your old verilog code (typically transactors) and add stuff like randomization and maybe coverage on top. Think Verification recommends, though, that you seriously consider a top-down approach as well (read: lose your old testbench), because a top-down approach provides a comprehensive solution to the verification problem. But today we're going to talk about the former approach which is a more pragmatic one in certain cases and we have a special guest for that.

 
Educate Yourself - SystemVerilog 101 PDF Print E-mail
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Sunday, 03 January 2010 14:22

SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get familiar with SystemVerilog unless you want to stay in the dark.

 
VMM Hackers Guide - Creating Smart Scenarios With Atomic Generators PDF Print E-mail
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Thursday, 24 December 2009 16:59

VMM ships with some pretty useful built-in components and applications. VMM''s Atomic Generator is probably one of the most powerful ones, yet it's pretty basic. It can definitely help you generate a flow of random items but it was not intended for generation of sequences. A sequence (a.k.a scenario) is a set of items that have some sort of correlation between them. For example - a set of 10 transactions with incremental addresses, or a set of 3 packets where the first one is always short and the last one is always long.

 
VMM Hackers Guide - Default Behavior For Your BFM PDF Print E-mail
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Thursday, 24 December 2009 16:58

Here's a short tutorial on how to implement a default behavior for your BFM using VMM.
Some protocols require constant activity on their interface even when you don't have any data to transmit. This means you must have a mechanism that drives idle packets or dummy data items as long as the generator doesn't produce items for its BFM. In VMM, Generators are connected to BFMs using vmm_channels and we''re just about to show you how to take advantage of that for our needs.

 
VMM Hackers Guide - Shutting Down Atomic Generators PDF Print E-mail
Thursday, 24 December 2009 16:57

Everybody likes atomic generators. If you have a vmm_data class, all you have to do is add a quick macro line and you get a free VMM-compliant generator that you only need to instantiate in your environment. An atomic generator is a simple yet powerful means to create a continuous flow of random data items to your DUT (more accurately “ to your BFM). Once everything is hooked up, all you have to do in your test program is set the number of items you want to generate, or let it run endlessly.

 
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