More articles : » Verification Documents - Love Them, Hate Them, But You Can't Ignore ThemVerification Plan (or Test Plan) and Coverage Plan are two documents that specify the features to be tested in the verification process. The first document usually lists the DUT features that need to be covered and the latter - the coverage points... » Cadence, Synopsys, Mentor - This Is Our Wish ListAs the EDA industry seems to be making moves towards a Unified Verification Methodology (OVM + VMM) we thought this would be a great opportunity to share a couple of things that have been on our wish-list for quite a while. » Progressive CoverageProgressive Coverage is a method of coverage collection that’s highly applicable in communication devices, but may as well be applied elsewhere. Now before I start to babble about my philosophy on coverage collection why don't I just give you an... » Educate Yourself - SystemVerilog 101SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get... » My Story With CertitudeLong time no see. My website has been down for a while (technical issues - web experts contact me if you want to help) but now it's up again. And going through some of my old articles here (well, they're all old, I should probably do something about... Copyright © 2017 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
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