Home Articles Main UVM Users: Here Are Some Great Tips [Video]

Search

UVM Users: Here Are Some Great Tips [Video] PDF Print E-mail
User Rating: / 19
PoorBest 
Friday, 15 June 2012 20:35

A couple of years ago I wrote here about how the UVM was becoming the next big thing in the verification world.

And guess what? I was right. Not that it was too hard to predict... but anyway, the industry has finally standardized on language (SV) and methodology (UVM) which is great news for us verification folks. The bad news is that even with SystemVerilog and UVM becoming ubiquitious, still we have to spend a fair amount of our time debugging our DUTs. And this is where the tools can be of much help.

 

 

Here are some cool tips for using DVE when you're debugging your UVM test bench.

Produced and narrated by yours truly, enjoy !

 

Dim lights Embed Embed this video on your site

 

Dim lights Embed Embed this video on your site

 

Dim lights Embed Embed this video on your site

 

 

 

Liked it? Check out all the other episodes of Cool Things You Can Do With DVE !

 

 

See ya!

 
More articles :

» Cadence, Synopsys, Mentor - This Is Our Wish List

As the EDA industry seems to be making moves towards a Unified Verification Methodology (OVM + VMM) we thought this would be a great opportunity to share a couple of things that have been on our wish-list for quite a while.

» Educate Yourself - SystemVerilog 101

SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get...

» My Story With Certitude

Long time no see. My website has been down for a while (technical issues - web experts contact me if you want to help) but now it's up again. And going through some of my old articles here (well, they're all old, I should probably do something about...

» The Easy Way To Start Using OVM-e Sequences

Industry-standard methodologies are great, really. It would be so nice if our entire verification environment (VE) were OVM-e (eRM) compliant, wouldn’t it? But what if there are legacy components in our env that don’t follow any specific...

» Verification Documents - Love Them, Hate Them, But You Can't Ignore Them

Verification Plan (or Test Plan) and Coverage Plan are two documents that specify the features to be tested in the verification process. The first document usually lists the DUT features that need to be covered and the latter - the coverage points...

Add comment


Security code
Refresh

Copyright © 2018 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.