Home SystemVerilog Latest Buzz From The EDA & Verification Community

Search

Latest Buzz From The EDA & Verification Community PDF Print E-mail
User Rating: / 4
PoorBest 
Thursday, 20 May 2010 08:57


 
More articles :

» Educate Yourself - SystemVerilog 101

SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get...

» Useful OVM-e Snippets

How to activate Specman Profiler? How to get rid of automatic vr_ad coverage? Let's find out.

» Coverage Driven Thoughts

In today’s short post what I’ll try to do is share with you some of the recent trends and ideas that deal with coverage. I won’t go into much technical detail today in order not to wear you (and myself) out, but really - if I want to be more...

» We Hear Ya!

 During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results: Verification Methodology - 41%SystemVerilog Tutorials - 31%e Tutorials - 13%Interviews - 12%...

» About UVM And You

There’s been a lot of buzz about the lately and for a reason. The Universal Verification Methodology is about to change the rules of the game pretty soon, if not already. That is interesting because not too long ago verification engineers...

Add comment


Security code
Refresh

Copyright © 2019 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.