More articles : » Packing In OVM-eThis example shows how to pack a struct into a list of Double Words (32 bit) keeping the original order. This time we got less talking, and more code: » Useful OVM-e SnippetsHow to activate Specman Profiler? How to get rid of automatic vr_ad coverage? Let's find out. » We Hear Ya! During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results: Verification Methodology - 41%SystemVerilog Tutorials - 31%e Tutorials - 13%Interviews - 12%... » Top Level Verification - What's The Big Deal?How to attack your chip from the top? Why is it so difficult to put together a good top level verification plan? Here are a few ideas. » Smart Constraints In SystemVerilogConstraints are our best friends when it comes to random generation. They allow us to limit the range of possible scenarios/values as much as we like, from the level of "everything is allowed" down to the level of such heavy constraints that really... Copyright © 2019 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
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