Home Articles Tips Don't Be SYSsy

Search

Don't Be SYSsy PDF Print E-mail
User Rating: / 0
PoorBest 
Thursday, 24 December 2009 15:26

Anyone who’s ever worked with me knows that I have several weaknesses. One of them is extra sensitivity to things that reside under sys (global.sys) in Specman/e. If this is Chinese to you then you’re probably a SystemVerilog guy: "sys" is the top most e struct (class) and the one struct people should strive NOT to use. The only thing that should be placed there is your own top unit, preferably customized to your project needs.

 

So the reason why people would want to use sys to place methods or other fields in the first place is because it’s accessible from everywhere, which is extremely convenient. But methodology-wise it would not be the smartest thing to do. Let me tell you why:

1. If you were the only verifier in your project then I would let you slip away. But since this is not the situation in most of the cases - you might get contentions on struct member names.

2. Placing code under sys encourages the use of full e paths rather than pointers and ports - code integration becomes a big mess this way, trust me.

3. Additional instances of your env is impossible because you can’t instantiate sys - no reuse.

4. You won’t be able to use your environment in a larger context because it’s not tightly encapsulated - no scalability.

5. There’s no logical distinction between the various elements, everything under the same struct - very hard to maintain

With all that being said - sometimes we need a speedy action and using sys could be a quick and dirty solution - that’s ok. But as a general guideline, unless you have a really good reason, don’t be syssy, create your own top level struct/unit, and use self-contained components.

 

 
More articles :

» Let The New Game Begin

Things are changing. The EDA industry is changing, and the verification world is changing (check out Janick Bergeron's inspiring at SNUG San Jose for a glimpse of the future of verification). One of the major challenges we’re already facing today...

» Eternal Sunshine of the Verifier's Mind

To be successful in verification you not only need to possess the right technical skills, but you also need to possess the right mindset. Possessing the right mindset will lead you to success rapidly. Here are 3 things that I’ve found very...

» VMM Hackers Guide - Creating Smart Scenarios With Atomic Generators

VMM ships with some pretty useful built-in components and applications. VMM''s Atomic Generator is probably one of the most powerful ones, yet it's pretty basic. It can definitely help you generate a flow of random items but it was not intended for...

» My Story With Certitude

Long time no see. My website has been down for a while (technical issues - web experts contact me if you want to help) but now it's up again. And going through some of my old articles here (well, they're all old, I should probably do something about...

» Debug Like The Pro's

You’ve developed a verification environment, hooked up the DUT, written a bunch of tests and alas! Simulations start to fail So just before you dive in, Think Verification’s tips department recommends the following:

Add comment


Security code
Refresh

Copyright © 2018 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.