Home Tips Don't Be SYSsy

Search

Don't Be SYSsy PDF Print E-mail
User Rating: / 0
PoorBest 
Thursday, 24 December 2009 15:26

Anyone who’s ever worked with me knows that I have several weaknesses. One of them is extra sensitivity to things that reside under sys (global.sys) in Specman/e. If this is Chinese to you then you’re probably a SystemVerilog guy: "sys" is the top most e struct (class) and the one struct people should strive NOT to use. The only thing that should be placed there is your own top unit, preferably customized to your project needs.

 

So the reason why people would want to use sys to place methods or other fields in the first place is because it’s accessible from everywhere, which is extremely convenient. But methodology-wise it would not be the smartest thing to do. Let me tell you why:

1. If you were the only verifier in your project then I would let you slip away. But since this is not the situation in most of the cases - you might get contentions on struct member names.

2. Placing code under sys encourages the use of full e paths rather than pointers and ports - code integration becomes a big mess this way, trust me.

3. Additional instances of your env is impossible because you can’t instantiate sys - no reuse.

4. You won’t be able to use your environment in a larger context because it’s not tightly encapsulated - no scalability.

5. There’s no logical distinction between the various elements, everything under the same struct - very hard to maintain

With all that being said - sometimes we need a speedy action and using sys could be a quick and dirty solution - that’s ok. But as a general guideline, unless you have a really good reason, don’t be syssy, create your own top level struct/unit, and use self-contained components.

 

 
More articles :

» VMM Hackers Guide - Default Behavior For Your BFM

Here's a short tutorial on how to implement a default behavior for your BFM using VMM. Some protocols require constant activity on their interface even when you don't have any data to transmit. This means you must have a mechanism that drives idle...

» UVM Users: Here Are Some Great Tips [Video]

A couple of years ago I wrote here about how the UVM was becoming the next big thing in the verification world.And guess what? I was right. Not that it was too hard to predict... but anyway, the industry has finally standardized on language (SV) and...

» About UVM And You

There’s been a lot of buzz about the lately and for a reason. The Universal Verification Methodology is about to change the rules of the game pretty soon, if not already. That is interesting because not too long ago verification engineers...

» Another Step Forward For VMM

While the move from 1.0 to 1.1 and its later flavors did not involve a major paradigm shift, VMM1.2 (beta) introduces several fundamentally new concepts that you should be aware of. Some of the new concepts are the natural result of an evolving...

» Review - Verification Leadership Seminar

How many of you have tried to cut on coffee? or even quit drinking coffee altogether? I guess a lot. Well, personally I’ve given up on trying but you know what? there’s actually something worse than having 8 cups of coffee per day - it’s the...

Add comment


Security code
Refresh

Copyright © 2017 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.