Home SystemVerilog We Hear Ya!

Search

We Hear Ya! PDF Print E-mail
User Rating: / 3
PoorBest 
Thursday, 08 April 2010 11:36

 

During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results:

 


Verification Methodology - 41%

SystemVerilog Tutorials - 31%

e Tutorials - 13%

Interviews - 12%

Lightweight Articles - 4%

Looks like most of you would like to learn more about advanced verification methodology, especially with SystemVerilog. That's a very clear message. We'll try to focus on that area in the coming months, and in the meantime we'd appreciate it if you could send us more specific requests (as some of you already have). You can also leave them as comments if you like.

In the meantime, if you haven't already seen our VMM Hackers Guide series, you might find it interesting.

And on that note - did you like our autodup utility? if you did, please drop us a line or leave a comment to encourage us to develop more stuff for you!

 

Oh, and have we ever mentioned how important t your feedback is to us? Wink

Seriously, even if you're not into the whole commenting thing please just devote 5 seconds of your time to take the poll (at the upper right of this page) to tell us what you think.

 

Happy Verifying!

 

 


 
More articles :

» Another Step Forward For VMM

While the move from 1.0 to 1.1 and its later flavors did not involve a major paradigm shift, VMM1.2 (beta) introduces several fundamentally new concepts that you should be aware of. Some of the new concepts are the natural result of an evolving...

» What Makes A Great Verification Team GREAT?

Your tool provider won’t tell you that, nor will those fancy methodology books, but verification is not all about mastering technical skills. True, those will help you very much in your daily work but verification is first and foremost TEAM WORK....

» Latest Buzz From The EDA & Verification Community

{loadposition pos101}{loadposition pos102}{loadposition pos103}{loadposition pos104}{loadposition pos105}{loadposition pos106}{loadposition pos107}{loadposition pos108}{loadposition pos109}{loadposition pos110}{loadposition pos111}{loadposition...

» DVT Eclipse - For SystemVerilog/Specman Code Developers

3 years ago that was on our wish list. Now it is a reality - A modern programming environment for verifiers!

» VMM Hackers Guide - Default Behavior For Your BFM

Here's a short tutorial on how to implement a default behavior for your BFM using VMM. Some protocols require constant activity on their interface even when you don't have any data to transmit. This means you must have a mechanism that drives idle...

Add comment


Security code
Refresh

Copyright © 2017 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.