More articles : » Method Manipulation In SV and eIf you're familiar with SystemVerilog and taking your first steps in e (or vice versa) you might find this useful. Here are some of the most common method manipulations that you''ll need to master and how you should go about implementing them in e... » VMM Hackers Guide - Creating Smart Scenarios With Atomic GeneratorsVMM ships with some pretty useful built-in components and applications. VMM''s Atomic Generator is probably one of the most powerful ones, yet it's pretty basic. It can definitely help you generate a flow of random items but it was not intended for... » Another Step Forward For VMMWhile the move from 1.0 to 1.1 and its later flavors did not involve a major paradigm shift, VMM1.2 (beta) introduces several fundamentally new concepts that you should be aware of. Some of the new concepts are the natural result of an evolving... » Don't Be SYSsyAnyone who’s ever worked with me knows that I have several weaknesses. One of them is extra sensitivity to things that reside under sys (global.sys) in Specman/e. If this is Chinese to you then you’re probably a SystemVerilog guy: "sys" is the... » UVM Users: Here Are Some Great Tips [Video]A couple of years ago I wrote here about how the UVM was becoming the next big thing in the verification world.And guess what? I was right. Not that it was too hard to predict... but anyway, the industry has finally standardized on language (SV) and... Copyright © 2018 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
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Thanks for posting comments on my website.
In my website, I also have OVM tutorial and Im in the process of posting more tutorials on OVM.
I regularly visit your site for advanced vmm stuff. Thanks for coming up with such a wonderful site.
Regards,
GopiKrishna
Author of www.testbench.in
I was unaware of couple of pointers. Now, I know ...
Looking forward to many more useful ones ....
Regards
Srinivas
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