Home Tips To Do List 2010


To Do List 2010 PDF Print E-mail
User Rating: / 4
Sunday, 03 January 2010 12:37
Introducing Philip Americus - a new guest blogger here on Think Verification. Phil is an ASIC veteran who's worked with every phase of ASIC design - from initial concept to tapeout, with an emphasis on verification, including management of both HW and SW engineers. This is his debut post on our website:

When I first started my Engineering career we had Verilog-95 and VHDL.  Combine this with some wrappers, in C, Perl, or Csh, and we accomplished Verification just fine.  As designs became larger and more complex, we continually felt a need to go to higher level programming models.  In came Specman, SystemVerilog (Superlog!), SystemC, model checking, etc. to meet the challenge. Some companies embraced these new technologies and some stuck with the old. 

My question is this:  Now that we are in 2010 (the Year We Make Contact, for those who get the movie reference), where do you think Verification technology will be, or should be, on January 1, 2011?  What big challenges do we face this year and how will we solve them?

1. Outsourcing - by the end of 2010 all small to medium sized companies will outsource all of their verification needs. Verification has become such a specialty that it will be more beneficial to the company to outsource it.  These verification companies would have several benefits over internal verification teams.  Their engineers would be super-specialists in high level verification.  They would also have at their disposal a large base of reusable test & environment code.  This would allow them to setup top level chip testing for a complex chip in an hour. Lastly, the outsourced verification company would have a large server farm. I have been at companies where we almost needed a full time manager/referee just to decide who gets to use which machine and for how long.

2. Say Goodbye To Design - by the end of 2010 all design teams are totally restructured.  These teams have all the design engineers replaced with software engineers who code the chip in C.  Then they bring in one ASIC Design Superman who takes all the code and converts into Verilog.  I say Design Superman, because this person has to really understand the limitations of both C and Verilog and how to make them work together correctly.

3. Database - The Verification environment should be built around a database. I think some of this capability is already available but it should be much simpler and easier to implement.  The test plan is created in the database, then the tests can be linked to the test plan, and the regression can also be linked into it.  This provides an easy way to monitor progress.  Also, for test re-use the database would require a check to see if the test still matches the requirement.  How many times have you written a test and forgot to see if it was still valid and/or actually did what it was supposed to do? The database would force you to check this detail.

Now it's your turn. What do you think about the year 2010?
More articles :

» Latest Buzz From The EDA & Verification Community

{loadposition pos101}{loadposition pos102}{loadposition pos103}{loadposition pos104}{loadposition pos105}{loadposition pos106}{loadposition pos107}{loadposition pos108}{loadposition pos109}{loadposition pos110}{loadposition pos111}{loadposition...

» Future Trends In HR

The industry is going through some tough times, no doubt about it. We’ve seen layoffs worldwide, projects being cancelled or put off for better times. How is this going to affect the way companies manage their human resources? Joining us today for...

» To Randomize Or Not To Randomize

One of my former colleagues once revealed the fact that she had no less than 70 pairs of shoes. That’s right, seventy! She had been very good at her job and by no means had any plans to start her own shoe business so I asked myself why on earth...

» Is ABV Becoming Mainstream?

Is Assertion-Based Verification (ABV) becoming mainstream? This question popped up today at Mentor’s ABV . Assertions in general and ABV in particular make another approach that you can use to verify your design. Usually ABV alone is not...

» Top Level Verification - What's The Big Deal?

How to attack your chip from the top? Why is it so difficult to put together a good top level verification plan? Here are a few ideas.


+1 #1 2010-01-05 17:24
I have some different opinions regarding the three wishes.

1. Writing the testbench and testcase is actually the easiest part in verification. The hardest part is coming up with a good testplan and debug the chip. That requires in-depth domain knowledge of the chip which is unique to each company.

I think each company should to keep a core verification team who knows about verification and the chip. Then hire contractors to do the implementation. The in-house team is the gate keeper to make sure the contractors did a good job verifying the chip.

Why would the outsourcing firms own huge server farms? Is it easier to rent CPU time from cloud provider during the peak time?
0 #2 2010-01-05 17:25
2. I doubt how much benefit we will get for writing RTL in C. It is a lot easier to learn Verilog than debug the funny RTL code generated from C and try to closing timing.

3. Cadence already has similar tool, EP and EM. We have been using it for over a year, it works great (minus the odd bugs here and there.)
0 #3 2010-01-07 15:15
Great points. But for 2. I think maybe it might take a bit longer time than you expected; And 1,3, sure, they are just happenning. But how about those verification team inside big companies? Is it reasonable for them to still keep such internal resource?
0 #4 2010-01-20 10:36
Quoting Horace Chan:
Why would the outsourcing firms own huge server farms? Is it easier to rent CPU time from cloud provider during the peak time?

The power of cloud computing is not only in servers. Cloud providers should provide ready to use systems.
Will cloud computing find a place in EDA industry?
Will it be possible to pay less money and rent ready to use EDA systems for a short periods (1, 2 weeks) instead of paying several 10k $ for full license?
If yes it will be a big help to low budget start ups and not only. But the important question is:
Will EDA companies like Synopsys and Cadence support cloud EDA providers?

Add comment

Security code

Copyright © 2019 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.