Home SystemVerilog Another Step Forward For VMM

Search

Another Step Forward For VMM PDF Print E-mail
User Rating: / 4
PoorBest 
Thursday, 24 December 2009 17:09

While the move from 1.0 to 1.1 and its later flavors did not involve a major paradigm shift, VMM1.2 (beta) introduces several fundamentally new concepts that you should be aware of. Some of the new concepts are the natural result of an evolving methodology, and others are probably features requested by VMM users who might have seen cool features in other languages and methodologies that had been missing in earlier versions of VMM.

 


The main new features are these:

· SystemC/SystemVerilog TLM 2.0 Support

o VMM Channel to TLM 2.0 interface

o Robust completion model

· Enhanced Block-to-Top Reuse

o Hierarchical phasing

o Class factory

o Hierarchical, structural, RTL configuration

· Enhanced Ease of Use

o Built-in phasing

o Serial-test phasing

o Parameterized channels and generators

o Common object and hierarchical name matching

 

One of the most interesting (and important) features that VMM1.2 gives you now is the built-in phasing. Let's try to explain this in simple words. A typical simulation should normally have several phases such as construct the objects, make inter-connections, start the DUT simulation, configure registers, drive transactions, finalize simulation, etc. Moreover, verification environments today usually consist of multiple components that should all be aware of that overall timeline unless you want chaos in your simulation (e.g. your CPU tries to write a register during initial reset phase and the packets scoreboard tries to wrap things up, report the number of mismatches and then go to sleep “ all occur at the same time).

Until now it was the sole responsibility of the top level class to orchestrate all this by explicitly activating the relevant functionality at the relevant phase for each of the sub elements. If you have some 20 sub environments in your top environment this translates into a lot of code and annoying oops I forgot to activate my xactor kind of bugs. VMM1.2 now allows you to implicitly activate the relevant functionality simply by extending a pre-defined method for each phase and thus avoid large portions of redundant code. What’s more, you can mix and match sub environments and components, each with its own so-called timeline mode (explicit or implicit).

Another cool feature of VMM1.2 would be the option to replace factory classes. You can read this for a complete explanation, but in simple words, it allows you to easily manipulate pre-defined classes from your test program. Being an Object Oriented language, the level of class manipulation that SystemVerilog allows is somewhat limited. The typical way to manipulate classes in SV is to define a new class that inherits from the original class, create an instance of the inherited class and then find all the places in your environment where the original is used and implant the new one at the right spot, in a procedural manner (rather than declaratively, which is easier). With a little bit of code overhead VMM1.2 now gives you a powerful way to simply replace the original factory class with a class of your own. Less effort, less code, less maintenance “ exactly what we like.

So VMM1.2 seems like a big step forward for SystemVerilog and we’ve only gone through 2 of the main new features. Be sure to check out the posts on VMMCentral and Verification Martial Arts to get more technical details so you don’t stay in the dark in this ever-changing world of verification methodology. But if you can''t wait to get your hands on it go here to sign up for the beta program

Editor's note: VMM1.2 is no longer "beta" (December 2009)

 

 

 

 

 

 

 

 

 

 
More articles :

» DVT Eclipse - For SystemVerilog/Specman Code Developers

3 years ago that was on our wish list. Now it is a reality - A modern programming environment for verifiers!

» Method Manipulation In SV and e

If you're familiar with SystemVerilog and taking your first steps in e (or vice versa) you might find this useful. Here are some of the most common method manipulations that you''ll need to master and how you should go about implementing them in e...

» EndMaker: Make Your SystemVerilog Code Look Professional (Free Utility)

This is a cool little utility that will make your SystemVerilog look much more professional. It simply adds an end-of-method identifier (label) to every task or function so that every endfunction turns into endfunction : function_name (with the...

» Cool Things You Can Do with Verdi

Wow it's been a while, but I'm back with a new series of YouTube videos. Hurray !!This time it's all about Verdi and all the cool things it can do for you.Since most of you guys already know it is the best debugger out there, my goal is to show you...

» We Hear Ya!

 During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results: Verification Methodology - 41%SystemVerilog Tutorials - 31%e Tutorials - 13%Interviews - 12%...

Add comment


Security code
Refresh

Copyright © 2017 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.