Home Articles SystemVerilog VMM Hackers Guide - Default Behavior For Your BFM

Search

VMM Hackers Guide - Default Behavior For Your BFM PDF Print E-mail
User Rating: / 7
PoorBest 
Thursday, 24 December 2009 16:58

Here's a short tutorial on how to implement a default behavior for your BFM using VMM.
Some protocols require constant activity on their interface even when you don't have any data to transmit. This means you must have a mechanism that drives idle packets or dummy data items as long as the generator doesn't produce items for its BFM. In VMM, Generators are connected to BFMs using vmm_channels and we''re just about to show you how to take advantage of that for our needs.

Note: Basic familiarity with SystemVerilog and VMM is assumed.

task bfm_main();
 forever begin
 // NON-DEFAULT BEHAVIOR: check if there''s anything waiting in the channel
 if (chan.size() > 0) begin 
 this.notify.reset(DONE);
 chan.get(packet);
 
 drive_packet(packet);
 
 // DEFAULT BFM BEHAVIOR: if channel is empty, drive an idle packet
 end else begin
 drive_idle_packet();
 end
 // and.. don''t forget to provide stopping condition
 wait_if_stopped(); 
 end
 endtask

 

 
More articles :

» VMM Hackers Guide - Creating Smart Scenarios With Atomic Generators

VMM ships with some pretty useful built-in components and applications. VMM''s Atomic Generator is probably one of the most powerful ones, yet it's pretty basic. It can definitely help you generate a flow of random items but it was not intended for...

» Another Step Forward For VMM

While the move from 1.0 to 1.1 and its later flavors did not involve a major paradigm shift, VMM1.2 (beta) introduces several fundamentally new concepts that you should be aware of. Some of the new concepts are the natural result of an evolving...

» We Hear Ya!

 During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results: Verification Methodology - 41%SystemVerilog Tutorials - 31%e Tutorials - 13%Interviews - 12%...

» Using Constrained-Random Verification with Legacy Testbenches

One of SystemVerilog's noticeable features is that it is basically a "design language" that has been extended with verification capabilities. This might be an advantage or not, depending on who you're asking, but obviously, if you only want to use a...

» VMM Hackers Guide - Shutting Down Atomic Generators

Everybody likes atomic generators. If you have a vmm_data class, all you have to do is add a quick macro line and you get a free VMM-compliant generator that you only need to instantiate in your environment. An atomic generator is a simple yet...

Comments  

 
0 #1 2010-12-12 11:24
verry good
Quote
 

Add comment


Security code
Refresh

Copyright © 2017 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.