Home Articles SystemVerilog VMM Hackers Guide - Default Behavior For Your BFM

Search

VMM Hackers Guide - Default Behavior For Your BFM PDF Print E-mail
User Rating: / 7
PoorBest 
Thursday, 24 December 2009 16:58

Here's a short tutorial on how to implement a default behavior for your BFM using VMM.
Some protocols require constant activity on their interface even when you don't have any data to transmit. This means you must have a mechanism that drives idle packets or dummy data items as long as the generator doesn't produce items for its BFM. In VMM, Generators are connected to BFMs using vmm_channels and we''re just about to show you how to take advantage of that for our needs.

Note: Basic familiarity with SystemVerilog and VMM is assumed.

task bfm_main();
 forever begin
 // NON-DEFAULT BEHAVIOR: check if there''s anything waiting in the channel
 if (chan.size() > 0) begin 
 this.notify.reset(DONE);
 chan.get(packet);
 
 drive_packet(packet);
 
 // DEFAULT BFM BEHAVIOR: if channel is empty, drive an idle packet
 end else begin
 drive_idle_packet();
 end
 // and.. don''t forget to provide stopping condition
 wait_if_stopped(); 
 end
 endtask

 

 
More articles :

» Method Manipulation In SV and e

If you're familiar with SystemVerilog and taking your first steps in e (or vice versa) you might find this useful. Here are some of the most common method manipulations that you''ll need to master and how you should go about implementing them in e...

» About UVM And You

There’s been a lot of buzz about the lately and for a reason. The Universal Verification Methodology is about to change the rules of the game pretty soon, if not already. That is interesting because not too long ago verification engineers...

» Cool Things You Can Do with Verdi

Wow it's been a while, but I'm back with a new series of YouTube videos. Hurray !!This time it's all about Verdi and all the cool things it can do for you.Since most of you guys already know it is the best debugger out there, my goal is to show you...

» We Hear Ya!

 During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results: Verification Methodology - 41%SystemVerilog Tutorials - 31%e Tutorials - 13%Interviews - 12%...

» VMM Hackers Guide - Shutting Down Atomic Generators

Everybody likes atomic generators. If you have a vmm_data class, all you have to do is add a quick macro line and you get a free VMM-compliant generator that you only need to instantiate in your environment. An atomic generator is a simple yet...

Comments  

 
0 #1 2010-12-12 11:24
verry good
Quote
 

Add comment


Security code
Refresh

Copyright © 2017 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.