Home SystemVerilog Useful OVM-e Snippets

Search

Useful OVM-e Snippets PDF Print E-mail
User Rating: / 10
PoorBest 
Thursday, 24 December 2009 16:41

How to activate Specman Profiler? How to get rid of automatic vr_ad coverage? Let's find out.

 

How to activate Specman Profiler?

extend sys {
setup() is also {
specman("set profile");
};
};

 

 

How to get rid of automatic vr_ad coverage?

extend sys {
setup() is also {
set_cover("vr_ad_reg", FALSE);
};
};

 

 

How to continue simulation regardless of DUT errors?

extend sys {
setup() is also {
set_check( "...", ERROR_CONTINUE );
// set_check( "...", IGNORE );  -- use this to disable DUT errors completely
};
};

 

 

How to instantiate a logger?

extend your_unit {
logger: message_logger is instance;
keep soft logger.verbosity == MEDIUM;
keep soft logger.tags == {NORMAL};
short_name(): string is {
result = append("YOUR_UNIT_NAME"); // can also be a dedicated evc_name
};
// Constrain the output coloring for better visibility
short_name_style(): vt_style is {
result = BLUE;
};
};

 

 

How to generate a random list of numbers?

gen_random_list_of_numbers(num_of_items: uint, max_val: uint): list of uint is {
assert num_of_items <= max_val + 1;
var next_item: uint;
for i from 1 to num_of_items {
gen next_item keeping {
it <= max_val;
it not in result;
};
result.add(next_item);
};
result = result.sort(it);
};



How to implement register side affect with vr_ad?

extend MY_REG vr_ad_reg {
post_access(direction : vr_ad_rw_t) is {
if direction == WRITE then { // or READ
// get pointer to the enclosing reg file
var rgf := get_parents()[0].as_a(REG_FILE_TYPE vr_ad_reg_file);
// side affect
if bit0 == 1 then {
rgf.another_register.another_bit = 1;
};
};
};
};

 

 

How to control generation of Boolean variables elegantly?

gen_true_or_false(true_prob: uint): bool is {
assert that true_prob <= 100;
gen result keeping {
soft it == select {
true_prob      : TRUE;
(100-true_prob): FALSE;
};
};
};

 

 

How to declare a sequence?

sequence my_prefix_seq_s using
item = my_prefix_frame_s,
created_kind   = my_prefix_seq_kind_t,
created_driver = my_prefix_driver_u,
sequence_type  = my_prefix_any_sequence_s,  // optional
sequence_driver_type = my_prefix_any_sequence_driver_u; // optional

 

 

How to use method ports?

struct packet {
just_a_number: uint;
};
// define a method type
 method_type packet_method_t (p: packet);
// add an output port
unit tx_u {
broadcast_packet: out method_port of packet_method_t is instance;
send_packet_to_port() is {
broadcast_packet$(pkt);
};
};
// add an input port
unit rx_u {
receive_packet: in method_port of packet_method_t is instance;

 receive_packet(p :packet)  is {
message(LOW,"packet received");
print p using hex;
};
};
//make a one-to-many connection
extend sys {
tx: tx_u is instance;
rx_list[2] : list of rx_u is instance;

 connect_ports() is also {
for each in rx_list {
do_bind(tx.broadcast_packet, it.receive_packet);
};
};
};
 

 

 
More articles :

» Is ABV Becoming Mainstream?

Is Assertion-Based Verification (ABV) becoming mainstream? This question popped up today at Mentor’s ABV . Assertions in general and ABV in particular make another approach that you can use to verify your design. Usually ABV alone is not...

» DVT Eclipse - For SystemVerilog/Specman Code Developers

3 years ago that was on our wish list. Now it is a reality - A modern programming environment for verifiers!

» How To Validate Type-Casting In OVM-e

Before type-casting an e variable ("as_a"), we often want to check the validity of the operation (this is quite similar in concept to $cast in SystenVerilog). The reason is simple, in case the casting operation failed we would end up with a fatal...

» Educate Yourself - SystemVerilog 101

SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get...

» AutoDup: Create Test Variants Quickly (Free Utility)

Coverage driven verification has a big advantage – you can write a single test, and let run it several times with random seeds. Each run will generate a slightly different scenario – depending on the nature of the constraints you provided....

Comments  

 
0 #1 2011-05-26 17:14
in e 9.2 - it is better to use the connect() pseudo method to connect method ports - thus solve the "star topology" issues
Quote
 

Add comment


Security code
Refresh

Copyright © 2017 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.