Home Specman / e Packing In OVM-e

Search

Packing In OVM-e PDF Print E-mail
User Rating: / 0
PoorBest 
Thursday, 24 December 2009 16:40

This example shows how to pack a struct into a list of Double Words (32 bit) keeping the original order. This time we got less talking, and more code:

 

 

Here's our struct:

struct my_struct_s { %byte1: byte;
 %word1: uint(bits: 16);
 %byte2: byte;
 %byte3: byte;
 %byte4: byte;
 %data1: uint(bits:11);
 %dword1: uint(bits: 32);
 %data2: uint(bits: 5);
keep byte1 == 0x12;
 keep word1 == 0x3456;
 keep byte2 == 0x78;
 keep byte3 == 0x9a;
 keep byte4 == 0xff;
 keep data1 == 11''b10101010101;
 keep dword1 == 32''b01010111111111111111101010101010;
 keep data2 == 5''b10101;
 };

Let's instantiate it and pack it:

extend sys { my_struct: my_struct_s;
 run() is also {
 print my_struct using hex; // just for reference
 var my_list: list of uint(bits:32);
 my_list = pack(packing.high, my_struct);  // stage 1, pack
 my_list = my_list.reverse(); // stage 2, reverse to restore original order
 print my_list using hex;
 }; 
};


And here's what the output should look like, note that the list reflects the original bit order


my_struct = my_struct_s-@0: my_struct_s
----------------------------------------------  @temp
0       %byte1:                         0x12
1       %word1:                         0x3456
2       %byte2:                         0x78
3       %byte3:                         0x9a
4       %byte4:                         0xff
5       %data1:                         0x555
6       %dword1:                        0x57fffaaa
7       %data2:                         0x15
my_list =
0.      12345678
1.      9affaaaa
2.      ffff5555
No actual running requested.
Checking the test ...
Checking is complete - 0 DUT errors, 0 DUT warnings.

 

 
More articles :

» The Cost Of Verification

We spend about one third of our lives in bed, right? doesn’t it make sense then to buy a good bed and not a cheap one? The same can be said for your verification tools as you spend so much of your project time on verification. Buying cheaper tools...

» Educate Yourself - SystemVerilog 101

SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get...

» Another Step Forward For VMM

While the move from 1.0 to 1.1 and its later flavors did not involve a major paradigm shift, VMM1.2 (beta) introduces several fundamentally new concepts that you should be aware of. Some of the new concepts are the natural result of an evolving...

» To Randomize Or Not To Randomize

One of my former colleagues once revealed the fact that she had no less than 70 pairs of shoes. That’s right, seventy! She had been very good at her job and by no means had any plans to start her own shoe business so I asked myself why on earth...

» Top Level Verification - What's The Big Deal?

How to attack your chip from the top? Why is it so difficult to put together a good top level verification plan? Here are a few ideas.

Add comment


Security code
Refresh

Copyright © 2018 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.