Home SystemVerilog Packing In OVM-e

Search

Packing In OVM-e PDF Print E-mail
User Rating: / 0
PoorBest 
Thursday, 24 December 2009 16:40

This example shows how to pack a struct into a list of Double Words (32 bit) keeping the original order. This time we got less talking, and more code:

 

 

Here's our struct:

struct my_struct_s { %byte1: byte;
 %word1: uint(bits: 16);
 %byte2: byte;
 %byte3: byte;
 %byte4: byte;
 %data1: uint(bits:11);
 %dword1: uint(bits: 32);
 %data2: uint(bits: 5);
keep byte1 == 0x12;
 keep word1 == 0x3456;
 keep byte2 == 0x78;
 keep byte3 == 0x9a;
 keep byte4 == 0xff;
 keep data1 == 11''b10101010101;
 keep dword1 == 32''b01010111111111111111101010101010;
 keep data2 == 5''b10101;
 };

Let's instantiate it and pack it:

extend sys { my_struct: my_struct_s;
 run() is also {
 print my_struct using hex; // just for reference
 var my_list: list of uint(bits:32);
 my_list = pack(packing.high, my_struct);  // stage 1, pack
 my_list = my_list.reverse(); // stage 2, reverse to restore original order
 print my_list using hex;
 }; 
};


And here's what the output should look like, note that the list reflects the original bit order


my_struct = my_struct_s-@0: my_struct_s
----------------------------------------------  @temp
0       %byte1:                         0x12
1       %word1:                         0x3456
2       %byte2:                         0x78
3       %byte3:                         0x9a
4       %byte4:                         0xff
5       %data1:                         0x555
6       %dword1:                        0x57fffaaa
7       %data2:                         0x15
my_list =
0.      12345678
1.      9affaaaa
2.      ffff5555
No actual running requested.
Checking the test ...
Checking is complete - 0 DUT errors, 0 DUT warnings.

 

 
More articles :

» What Is Functional Qualification?

Mark Hampton, CTO and Co-founder of is joining us today here on Think Verification to give us a glimpse of what Functional Qualification, a breakthrough in the concept of a complete verification environment, is all about. So without further ado -...

» Get Organized Even On Windows

Here’s a cool (and free) application that can make your life a bit more organized if you tend to have many open windows.

» DVT Eclipse - For SystemVerilog/Specman Code Developers

3 years ago that was on our wish list. Now it is a reality - A modern programming environment for verifiers!

» UVM Users: Here Are Some Great Tips [Video]

A couple of years ago I wrote here about how the UVM was becoming the next big thing in the verification world.And guess what? I was right. Not that it was too hard to predict... but anyway, the industry has finally standardized on language (SV) and...

» Smart Constraints In SystemVerilog

Constraints are our best friends when it comes to random generation. They allow us to limit the range of possible scenarios/values as much as we like, from the level of "everything is allowed" down to the level of such heavy constraints that really...

Add comment


Security code
Refresh

Copyright © 2019 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.