Home SystemVerilog Specman Compiled Mode

Search

Specman Compiled Mode PDF Print E-mail
User Rating: / 8
PoorBest 
Thursday, 24 December 2009 15:18

This is a really short tutorial that demonstrates the entire process of compiling and running a simulation with NC-Verilog & Specman (using compiled specman).

 

Consider the following sample design - my_xor.v:

module my_xor (A,B,Y);
    input A;
    input B;
    output Y;
    assign Y = A ^ B;
endmodule


A very complex DUT as you may have noticed.

Now let’s add the environment - env.e:

 
extend sys {
   run() is also {
        start my_test();
    };
    my_test()@sys.any is {
       out( ==== START ,sys.time);
       wait delay (1000 ns);
       ’~/my_xor/A’ = 1;
       ’~/my_xor/B’ = 0;
       wait delay (1000 ns);
       ’~/my_xor/A’ = 0;
       wait delay (1000 ns);
       out( ==== END ,sys.time);
    };
};
 


It’s a just a quick demo env so excuse the coding style. And now for the fun part - Let’s simulate our little environment with the DUT - 
Open a fresh terminal and make sure you got the 2 files at your current dir (copy & paste into my_xor.v and env.e) and follow these steps:

1. First , compile the e code into a shared library so that an executable file is created and also a corresponding esv file:
%sn_compile.sh -shlib -exe env.e

2. Use the newly created executable file (env) to create verilog stubs file:
%./env -c write stubs -ncvlog

3. Compile the verilog code plus the newly created stub file (specman.v):
%ncvlog -MESSAGES -UPDATE my_xor.v specman.v

4.  Elaborate the design:
%ncelab_specman specman my_xor -snapshot my_xor -access +rwc

5. Now you have to tell Specman where to find the compilation results
%setenv SPECMAN_DLIB ./libsn_env.so

6. That’s is - now run the simulation:
%specrun -p test ncsim -nbasync my_xor

As usual, read the manual to get the full picture but the example above should give you the hang of it and may be used as reference. And if you were wondering if there was a single script solution for this, well - there is. Cadence recently released the irun script which should take care of everything you always wanted from your simulator but were afraid to ask. Quite a catchy name for a script, don’t you think?

 

 
More articles :

» Ignorance Is A Bliss

There is a rather confusing feature in Specman’s coverage engine that I would like to share with you today. I’ve met several people (including myself) who had been struggling to understand what was going on there and gave up Recently I was...

» Smart Constraints In SystemVerilog

Constraints are our best friends when it comes to random generation. They allow us to limit the range of possible scenarios/values as much as we like, from the level of "everything is allowed" down to the level of such heavy constraints that really...

» Read/Write Registers From Everywhere

Here’s something for the less experienced verifiers out there. I’ve been asked to help with this issue several times in the past so I guess some of you will find it useful.

» Cadence, Synopsys, Mentor - This Is Our Wish List

As the EDA industry seems to be making moves towards a Unified Verification Methodology (OVM + VMM) we thought this would be a great opportunity to share a couple of things that have been on our wish-list for quite a while.

» Don't Be SYSsy

Anyone who’s ever worked with me knows that I have several weaknesses. One of them is extra sensitivity to things that reside under sys (global.sys) in Specman/e. If this is Chinese to you then you’re probably a SystemVerilog guy: "sys" is the...

Comments  

 
0 #1 2010-01-02 04:54
The indent seems broken in the 2nd piece of code.
Quote
 
 
0 #2 2010-01-02 06:06
Thanks Horace! Fixed.
Quote
 

Add comment


Security code
Refresh

Copyright © 2019 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.