Home Specman / e Specman Compiled Mode

Search

Specman Compiled Mode PDF Print E-mail
User Rating: / 8
PoorBest 
Thursday, 24 December 2009 15:18

This is a really short tutorial that demonstrates the entire process of compiling and running a simulation with NC-Verilog & Specman (using compiled specman).

 

Consider the following sample design - my_xor.v:

module my_xor (A,B,Y);
    input A;
    input B;
    output Y;
    assign Y = A ^ B;
endmodule


A very complex DUT as you may have noticed.

Now let’s add the environment - env.e:

 
extend sys {
   run() is also {
        start my_test();
    };
    my_test()@sys.any is {
       out( ==== START ,sys.time);
       wait delay (1000 ns);
       ’~/my_xor/A’ = 1;
       ’~/my_xor/B’ = 0;
       wait delay (1000 ns);
       ’~/my_xor/A’ = 0;
       wait delay (1000 ns);
       out( ==== END ,sys.time);
    };
};
 


It’s a just a quick demo env so excuse the coding style. And now for the fun part - Let’s simulate our little environment with the DUT - 
Open a fresh terminal and make sure you got the 2 files at your current dir (copy & paste into my_xor.v and env.e) and follow these steps:

1. First , compile the e code into a shared library so that an executable file is created and also a corresponding esv file:
%sn_compile.sh -shlib -exe env.e

2. Use the newly created executable file (env) to create verilog stubs file:
%./env -c write stubs -ncvlog

3. Compile the verilog code plus the newly created stub file (specman.v):
%ncvlog -MESSAGES -UPDATE my_xor.v specman.v

4.  Elaborate the design:
%ncelab_specman specman my_xor -snapshot my_xor -access +rwc

5. Now you have to tell Specman where to find the compilation results
%setenv SPECMAN_DLIB ./libsn_env.so

6. That’s is - now run the simulation:
%specrun -p test ncsim -nbasync my_xor

As usual, read the manual to get the full picture but the example above should give you the hang of it and may be used as reference. And if you were wondering if there was a single script solution for this, well - there is. Cadence recently released the irun script which should take care of everything you always wanted from your simulator but were afraid to ask. Quite a catchy name for a script, don’t you think?

 

 
More articles :

» Get On The Buss

Wow, it’s been a while since we last had a good old techie talk about Specman so why not now? Today I’d like to focus on applying reuse to Specman external ports. Very much like little caterpillars, DUTs often have tens or even hundreds of pins...

» Another Step Forward For VMM

While the move from 1.0 to 1.1 and its later flavors did not involve a major paradigm shift, VMM1.2 (beta) introduces several fundamentally new concepts that you should be aware of. Some of the new concepts are the natural result of an evolving...

» About UVM And You

There’s been a lot of buzz about the lately and for a reason. The Universal Verification Methodology is about to change the rules of the game pretty soon, if not already. That is interesting because not too long ago verification engineers...

» Progressive Coverage

Progressive Coverage is a method of coverage collection that’s highly applicable in communication devices, but may as well be applied elsewhere. Now before I start to babble about my philosophy on coverage collection why don't I just give you an...

» Educate Yourself - SystemVerilog 101

SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get...

Comments  

 
0 #1 2010-01-02 04:54
The indent seems broken in the 2nd piece of code.
Quote
 
 
0 #2 2010-01-02 06:06
Thanks Horace! Fixed.
Quote
 

Add comment


Security code
Refresh

Copyright © 2018 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.