Home Specman / e Specman Compiled Mode

Search

Specman Compiled Mode PDF Print E-mail
User Rating: / 8
PoorBest 
Thursday, 24 December 2009 15:18

This is a really short tutorial that demonstrates the entire process of compiling and running a simulation with NC-Verilog & Specman (using compiled specman).

 

Consider the following sample design - my_xor.v:

module my_xor (A,B,Y);
    input A;
    input B;
    output Y;
    assign Y = A ^ B;
endmodule


A very complex DUT as you may have noticed.

Now let’s add the environment - env.e:

 
extend sys {
   run() is also {
        start my_test();
    };
    my_test()@sys.any is {
       out( ==== START ,sys.time);
       wait delay (1000 ns);
       ’~/my_xor/A’ = 1;
       ’~/my_xor/B’ = 0;
       wait delay (1000 ns);
       ’~/my_xor/A’ = 0;
       wait delay (1000 ns);
       out( ==== END ,sys.time);
    };
};
 


It’s a just a quick demo env so excuse the coding style. And now for the fun part - Let’s simulate our little environment with the DUT - 
Open a fresh terminal and make sure you got the 2 files at your current dir (copy & paste into my_xor.v and env.e) and follow these steps:

1. First , compile the e code into a shared library so that an executable file is created and also a corresponding esv file:
%sn_compile.sh -shlib -exe env.e

2. Use the newly created executable file (env) to create verilog stubs file:
%./env -c write stubs -ncvlog

3. Compile the verilog code plus the newly created stub file (specman.v):
%ncvlog -MESSAGES -UPDATE my_xor.v specman.v

4.  Elaborate the design:
%ncelab_specman specman my_xor -snapshot my_xor -access +rwc

5. Now you have to tell Specman where to find the compilation results
%setenv SPECMAN_DLIB ./libsn_env.so

6. That’s is - now run the simulation:
%specrun -p test ncsim -nbasync my_xor

As usual, read the manual to get the full picture but the example above should give you the hang of it and may be used as reference. And if you were wondering if there was a single script solution for this, well - there is. Cadence recently released the irun script which should take care of everything you always wanted from your simulator but were afraid to ask. Quite a catchy name for a script, don’t you think?

 

 
More articles :

» Educate Yourself - SystemVerilog 101

SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get...

» Verification Consulting, What's Next?

Will the demand for Design and Verification services change? How will Functional Verification look like 3 years from now? Think Verification caught Cristian Amitroaie, AMIQ’s CEO, for a quick chat.

» VMM Hackers Guide - Shutting Down Atomic Generators

Everybody likes atomic generators. If you have a vmm_data class, all you have to do is add a quick macro line and you get a free VMM-compliant generator that you only need to instantiate in your environment. An atomic generator is a simple yet...

» What Is Functional Qualification?

Mark Hampton, CTO and Co-founder of is joining us today here on Think Verification to give us a glimpse of what Functional Qualification, a breakthrough in the concept of a complete verification environment, is all about. So without further ado -...

» The Easy Way To Start Using OVM-e Sequences

Industry-standard methodologies are great, really. It would be so nice if our entire verification environment (VE) were OVM-e (eRM) compliant, wouldn’t it? But what if there are legacy components in our env that don’t follow any specific...

Comments  

 
0 #1 2010-01-02 04:54
The indent seems broken in the 2nd piece of code.
Quote
 
 
0 #2 2010-01-02 06:06
Thanks Horace! Fixed.
Quote
 

Add comment


Security code
Refresh

Copyright © 2018 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.