Home Tips Specman Compiled Mode


Specman Compiled Mode PDF Print E-mail
User Rating: / 8
Thursday, 24 December 2009 15:18

This is a really short tutorial that demonstrates the entire process of compiling and running a simulation with NC-Verilog & Specman (using compiled specman).


Consider the following sample design - my_xor.v:

module my_xor (A,B,Y);
    input A;
    input B;
    output Y;
    assign Y = A ^ B;

A very complex DUT as you may have noticed.

Now let’s add the environment - env.e:

extend sys {
   run() is also {
        start my_test();
    my_test()@sys.any is {
       out( ==== START ,sys.time);
       wait delay (1000 ns);
       ’~/my_xor/A’ = 1;
       ’~/my_xor/B’ = 0;
       wait delay (1000 ns);
       ’~/my_xor/A’ = 0;
       wait delay (1000 ns);
       out( ==== END ,sys.time);

It’s a just a quick demo env so excuse the coding style. And now for the fun part - Let’s simulate our little environment with the DUT - 
Open a fresh terminal and make sure you got the 2 files at your current dir (copy & paste into my_xor.v and env.e) and follow these steps:

1. First , compile the e code into a shared library so that an executable file is created and also a corresponding esv file:
%sn_compile.sh -shlib -exe env.e

2. Use the newly created executable file (env) to create verilog stubs file:
%./env -c write stubs -ncvlog

3. Compile the verilog code plus the newly created stub file (specman.v):
%ncvlog -MESSAGES -UPDATE my_xor.v specman.v

4.  Elaborate the design:
%ncelab_specman specman my_xor -snapshot my_xor -access +rwc

5. Now you have to tell Specman where to find the compilation results
%setenv SPECMAN_DLIB ./libsn_env.so

6. That’s is - now run the simulation:
%specrun -p test ncsim -nbasync my_xor

As usual, read the manual to get the full picture but the example above should give you the hang of it and may be used as reference. And if you were wondering if there was a single script solution for this, well - there is. Cadence recently released the irun script which should take care of everything you always wanted from your simulator but were afraid to ask. Quite a catchy name for a script, don’t you think?


More articles :

» Plug, Play and Reuse!

Time to talk about module-to-system reuse, a very important topic. If you plan your verification environment properly (using one of the common methodologies in the market today or your own) you’ll be able to easily build a system level...

» UVM Users: Here Are Some Great Tips [Video]

A couple of years ago I wrote here about how the UVM was becoming the next big thing in the verification world.And guess what? I was right. Not that it was too hard to predict... but anyway, the industry has finally standardized on language (SV) and...

» The Easy Way To Start Using OVM-e Sequences

Industry-standard methodologies are great, really. It would be so nice if our entire verification environment (VE) were OVM-e (eRM) compliant, wouldn’t it? But what if there are legacy components in our env that don’t follow any specific...

» Let The New Game Begin

Things are changing. The EDA industry is changing, and the verification world is changing (check out Janick Bergeron's inspiring at SNUG San Jose for a glimpse of the future of verification). One of the major challenges we’re already facing today...

» What Makes A Great Verification Team GREAT?

Your tool provider won’t tell you that, nor will those fancy methodology books, but verification is not all about mastering technical skills. True, those will help you very much in your daily work but verification is first and foremost TEAM WORK....


0 #1 2010-01-02 04:54
The indent seems broken in the 2nd piece of code.
0 #2 2010-01-02 06:06
Thanks Horace! Fixed.

Add comment

Security code

Copyright © 2018 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.