Home Articles Specman-e The Easy Way To Start Using OVM-e Sequences

Search

The Easy Way To Start Using OVM-e Sequences PDF Print E-mail
User Rating: / 2
PoorBest 
Thursday, 24 December 2009 15:41

Industry-standard methodologies are great, really. It would be so nice if our entire verification environment (VE) were OVM-e (eRM) compliant, wouldn’t it? But what if there are legacy components in our env that don’t follow any specific methodology and we still want to make them speak OVM-e?

 

What we often want to do is take our legacy driver and monitor (or whatever TCMs that provide this functionality) and make them a nice self-contained Interface eVC with a Sequence mechanism and all that stuff. Now the good news is that usually this is not a big problem. So here are Think Verification’s 5 easy steps to start using sequences in your env:

1. Redefine your transaction - go back to your original transaction definition and make it inherit from any_sequence_item.

2. Get hold of another eVC that’s good for your application and extract its skeleton (delete all protocol-specific code but leave all units, struct method headers, interconnection). Alternatively, use a script such as vBuilder to build a skeleton for you. Think Verification strongly recommends changing all file and struct names to be consistent and add a unique prefix to all objects and types (very useful, also required by eRM rules). A small perl utility can help, try this.

3. Fill your monitor unit with protocol-specific content (e.g. implement the while TRUE loop in the main tcm).

4. Fill your BFM unit with protocol-specific content (e.g. implement the drive_transaction tcm).

5. Prepare a sample test file which extends the MAIN sequence and generates one or more items to test your new eVC.

And one final tip for writing new eVCs - Always have a known-to-be-good eVC nearby as reference!

Voila! Now you have a new eVC and you can send your legacy componets away to the National Museum of Verification History. It’s now time to develop your Sequence Library. Happy Sequencing!

 

 
More articles :

» Is ABV Becoming Mainstream?

Is Assertion-Based Verification (ABV) becoming mainstream? This question popped up today at Mentor’s ABV . Assertions in general and ABV in particular make another approach that you can use to verify your design. Usually ABV alone is not...

» Using Constrained-Random Verification with Legacy Testbenches

One of SystemVerilog's noticeable features is that it is basically a "design language" that has been extended with verification capabilities. This might be an advantage or not, depending on who you're asking, but obviously, if you only want to use a...

» Future Trends In HR

The industry is going through some tough times, no doubt about it. We’ve seen layoffs worldwide, projects being cancelled or put off for better times. How is this going to affect the way companies manage their human resources? Joining us today for...

» What Is Functional Qualification?

Mark Hampton, CTO and Co-founder of is joining us today here on Think Verification to give us a glimpse of what Functional Qualification, a breakthrough in the concept of a complete verification environment, is all about. So without further ado -...

» Don't Be SYSsy

Anyone who’s ever worked with me knows that I have several weaknesses. One of them is extra sensitivity to things that reside under sys (global.sys) in Specman/e. If this is Chinese to you then you’re probably a SystemVerilog guy: "sys" is the...

Add comment


Security code
Refresh

Copyright © 2017 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.