Home

Search

We Hear Ya! PDF Print E-mail
User Rating: / 3
PoorBest 
Thursday, 08 April 2010 11:36

 

During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results:

 


Verification Methodology - 41%

SystemVerilog Tutorials - 31%

e Tutorials - 13%

Interviews - 12%

Lightweight Articles - 4%

Looks like most of you would like to learn more about advanced verification methodology, especially with SystemVerilog. That's a very clear message. We'll try to focus on that area in the coming months, and in the meantime we'd appreciate it if you could send us more specific requests (as some of you already have). You can also leave them as comments if you like.

In the meantime, if you haven't already seen our VMM Hackers Guide series, you might find it interesting.

And on that note - did you like our autodup utility? if you did, please drop us a line or leave a comment to encourage us to develop more stuff for you!

 

Oh, and have we ever mentioned how important t your feedback is to us? Wink

Seriously, even if you're not into the whole commenting thing please just devote 5 seconds of your time to take the poll (at the upper right of this page) to tell us what you think.

 

Happy Verifying!

 

 


 
More articles :

» Using Constrained-Random Verification with Legacy Testbenches

One of SystemVerilog's noticeable features is that it is basically a "design language" that has been extended with verification capabilities. This might be an advantage or not, depending on who you're asking, but obviously, if you only want to use a...

» Let The New Game Begin

Things are changing. The EDA industry is changing, and the verification world is changing (check out Janick Bergeron's inspiring at SNUG San Jose for a glimpse of the future of verification). One of the major challenges we’re already facing today...

» Is ABV Becoming Mainstream?

Is Assertion-Based Verification (ABV) becoming mainstream? This question popped up today at Mentor’s ABV . Assertions in general and ABV in particular make another approach that you can use to verify your design. Usually ABV alone is not...

» Top Level Verification - What's The Big Deal?

How to attack your chip from the top? Why is it so difficult to put together a good top level verification plan? Here are a few ideas.

» Verification Documents - Love Them, Hate Them, But You Can't Ignore Them

Verification Plan (or Test Plan) and Coverage Plan are two documents that specify the features to be tested in the verification process. The first document usually lists the DUT features that need to be covered and the latter - the coverage points...

Add comment


Security code
Refresh

Copyright © 2019 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.