Home

Search

Specman GUI Trick PDF Print E-mail
User Rating: / 1
PoorBest 
Thursday, 24 December 2009 15:39

If you’re using Specman GUI to run simulations you must have encountered this rather annoying feature before - When running several simulations during the same session, specman doesn’t clear the log file by default so what you get in the end is a concatenation of all log files which makes it kind of - how to put it nicely -  useless.

 

Ok, now try adding this to your e testbench (the top most e file)

 

extend global {
setup_test() is also {
specman(set log off);
specman(set log specman.elog);
};
};

 

Voila!

 

 
More articles :

» Read/Write Registers From Everywhere

Here’s something for the less experienced verifiers out there. I’ve been asked to help with this issue several times in the past so I guess some of you will find it useful.

» Top 10 Verification Myths

Let’s unveil the truth behind some of the common myths out there!

» Smart Constraints In SystemVerilog

Constraints are our best friends when it comes to random generation. They allow us to limit the range of possible scenarios/values as much as we like, from the level of "everything is allowed" down to the level of such heavy constraints that really...

» We Hear Ya!

 During the last months we conducted a poll about what you guys would you like to read more about on ThinkVerification and here are the results: Verification Methodology - 41%SystemVerilog Tutorials - 31%e Tutorials - 13%Interviews - 12%...

» EndMaker: Make Your SystemVerilog Code Look Professional (Free Utility)

This is a cool little utility that will make your SystemVerilog look much more professional. It simply adds an end-of-method identifier (label) to every task or function so that every endfunction turns into endfunction : function_name (with the...

Add comment


Security code
Refresh

Copyright © 2019 Think Verification - Tips & Insights on ASIC Verification. All Rights Reserved.
Joomla! is Free Software released under the GNU/GPL License.