Think Verification - Tips & Insights on ASIC Verification Think Verification - Tips & Insights on ASIC Verification - trends, insights, tutorials, videos, tips, and lots of cool stuff http://thinkverification.com/index.php?option=com_content&view=frontpage Sun, 23 Apr 2017 21:41:13 +0000 Joomla! 1.5 - Open Source Content Management en-gb Cool Things You Can Do with Verdi http://thinkverification.com/index.php?option=com_content&view=article&id=72:cool-things-you-can-do-with-verdi&catid=1:main&Itemid=5 http://thinkverification.com/index.php?option=com_content&view=article&id=72:cool-things-you-can-do-with-verdi&catid=1:main&Itemid=5 Wow it's been a while, but I'm back with a new series of YouTube videos. Hurray !!

This time it's all about Verdi and all the cool things it can do for you.

Since most of you guys already know it is the best debugger out there, my goal is to show you other aspects of Verdi, primarily Coverage and Verification Planinng.

If you don't know what I'm talking about - you should definitely check this video out.

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admin@thinkverification.com (Administrator) frontpage Tue, 22 Jul 2014 15:32:07 +0000
My Story With Certitude http://thinkverification.com/index.php?option=com_content&view=article&id=71:my-story-with-certitude&catid=1:main&Itemid=5 http://thinkverification.com/index.php?option=com_content&view=article&id=71:my-story-with-certitude&catid=1:main&Itemid=5 Long time no see. My website has been down for a while (technical issues - web experts contact me if you want to help) but now it's up again. And going through some of my old articles here (well, they're all old, I should probably do something about it...) I came across an interview I did some 4 years ago with Mark Hampton, co-founder of Certess - the company that developed Certitude. For those who don't know - Certitude is a cool technology that verifies that your verification environment really does its job. I thought their technology was really exciting and could see how it might change the way verifiers thought about "verification closure".

Anyway, 4 years have passed and today I work at Synopsys who back in 2012 acquired this technology (through SpringSoft) . I can run Cerittude on my laptop and then go to lunch with a Certitude expert. That's what I call closure! 


I will make an effort to continue blogging, but I will need your help to keep me motivated. You can start by leaving a comment to share your thoughts on verification.

 

Oh - and if you want to catch up with Certitude - here's a great place to start.

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admin@thinkverification.com (Administrator) frontpage Fri, 26 Jul 2013 08:01:45 +0000
UVM Users: Here Are Some Great Tips [Video] http://thinkverification.com/index.php?option=com_content&view=article&id=68:uvm-users-here-are-some-great-tips-video&catid=1:main&Itemid=5 http://thinkverification.com/index.php?option=com_content&view=article&id=68:uvm-users-here-are-some-great-tips-video&catid=1:main&Itemid=5 A couple of years ago I wrote here about how the UVM was becoming the next big thing in the verification world.

And guess what? I was right. Not that it was too hard to predict... but anyway, the industry has finally standardized on language (SV) and methodology (UVM) which is great news for us verification folks. The bad news is that even with SystemVerilog and UVM becoming ubiquitious, still we have to spend a fair amount of our time debugging our DUTs. And this is where the tools can be of much help.

 

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admin@thinkverification.com (Administrator) frontpage Fri, 15 Jun 2012 20:35:44 +0000
Educate Yourself - SystemVerilog 101 http://thinkverification.com/index.php?option=com_content&view=article&id=49:educate-yourself-systemverilog-101&catid=6:systemverilog&Itemid=13 http://thinkverification.com/index.php?option=com_content&view=article&id=49:educate-yourself-systemverilog-101&catid=6:systemverilog&Itemid=13 SystemVerilog emerged a few years ago and has gained phenomenal popularity ever since. Today this language is virtually ubiquitous and all 3 big EDA vendors keep pushing it forward. So if you consider yourself a modern verifier, you'd better get familiar with SystemVerilog unless you want to stay in the dark.

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admin@thinkverification.com (Administrator) frontpage Sun, 03 Jan 2010 14:22:56 +0000
About UVM And You http://thinkverification.com/index.php?option=com_content&view=article&id=53:about-uvm-and-you&catid=1:main&Itemid=5 http://thinkverification.com/index.php?option=com_content&view=article&id=53:about-uvm-and-you&catid=1:main&Itemid=5 There’s been a lot of buzz about the UVM lately and for a reason. The Universal Verification Methodology is about to change the rules of the game pretty soon, if not already. That is interesting because not too long ago verification engineers questioned the need for adopting any verification methodology… Today, however, the question is entirely different – it is WHICH methodology to adopt. So as the UVM is gradually taking form and drawing the attention of verification stakeholders I think it’s a great time to stop and remind ourselves why we need a verification methodology in the first place, and more importantly - what makes a verification methodology so good that the only question about it would be “how quickly can I learn it”?  I have identified 3 elements of a good verification methodology that work together, each on a separate track, to make it do its magic. The first element is Guidance, the second is Efficiency, and the third one – perhaps the most exciting one – is what I call The Real Added Value.

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admin@thinkverification.com (Administrator) frontpage Mon, 01 Mar 2010 16:52:01 +0000
Let The New Game Begin http://thinkverification.com/index.php?option=com_content&view=article&id=66:let-the-new-game-begin&catid=1:main&Itemid=5 http://thinkverification.com/index.php?option=com_content&view=article&id=66:let-the-new-game-begin&catid=1:main&Itemid=5 Things are changing. The EDA industry is changing, and the verification world is changing (check out Janick Bergeron's inspiring talk at SNUG San Jose for a glimpse of the future of verification). One of the major challenges we’re already facing today is an increasing number of IP blocks in a single system. Designs are getting bigger and bigger, and the focus is shifting towards system level integration rather than “design creation”.

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admin@thinkverification.com (Administrator) frontpage Mon, 07 Jun 2010 14:02:12 +0000
Is ABV Becoming Mainstream? http://thinkverification.com/index.php?option=com_content&view=article&id=60:is-abv-becoming-mainstream&catid=2:reviews&Itemid=10 http://thinkverification.com/index.php?option=com_content&view=article&id=60:is-abv-becoming-mainstream&catid=2:reviews&Itemid=10 Is Assertion-Based Verification (ABV) becoming mainstream? This question popped up today at Mentor’s ABV seminar. Assertions in general and ABV in particular make another approach that you can use to verify your design. Usually ABV alone is not sufficient, and is used alongside other verification approaches such as Coverage-Driven Verification, Directed Testing, Formal Verification, and Code Coverage. What’s good about ABV though, is that it’s the fastest tool around in terms of failure-to-root-cause time (also in your testbench!)

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admin@thinkverification.com (Administrator) frontpage Sun, 25 Apr 2010 13:06:02 +0000
EndMaker: Make Your SystemVerilog Code Look Professional (Free Utility) http://thinkverification.com/index.php?option=com_content&view=article&id=59:endmaker-make-your-systemverilog-code-look-professional-free-utility&catid=5:tips&Itemid=11 http://thinkverification.com/index.php?option=com_content&view=article&id=59:endmaker-make-your-systemverilog-code-look-professional-free-utility&catid=5:tips&Itemid=11 This is a cool little utility that will make your SystemVerilog look much more professional. It simply adds an end-of-method identifier (label) to every task or function so that every endfunction turns into endfunction : function_name (with the appropriate function_name of course.. Duh!) and endtask turns into endtask : task_name.  This really makes your code more readable and consistent.

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admin@thinkverification.com (Administrator) frontpage Thu, 15 Apr 2010 12:46:25 +0000
AutoDup: Create Test Variants Quickly (Free Utility) http://thinkverification.com/index.php?option=com_content&view=article&id=57:create-test-variants-quickly-free-utility-&catid=5:tips&Itemid=11 http://thinkverification.com/index.php?option=com_content&view=article&id=57:create-test-variants-quickly-free-utility-&catid=5:tips&Itemid=11 Coverage driven verification has a big advantage – you can write a single test, and let run it several times with random seeds. Each run will generate a slightly different scenario – depending on the nature of the constraints you provided. I’ve talked about the pros and cons of excessive use of coverage driven methods here and here. Anyway, sometimes you just want to take an existing test and quickly create a number of variants off of it to make a small regression suite (that you might even throw away later on). For example – you could have a basic test that does some CPU writes and then drives random frames. During configuration you write to a register that sets the FIFO level and you want to have 10 different tests, each writes a different value to this register.

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admin@thinkverification.com (Administrator) frontpage Thu, 01 Apr 2010 15:12:50 +0000
What Makes A Great Verification Team GREAT? http://thinkverification.com/index.php?option=com_content&view=article&id=37:what-makes-a-great-verification-team-great-&catid=1:main&Itemid=5 http://thinkverification.com/index.php?option=com_content&view=article&id=37:what-makes-a-great-verification-team-great-&catid=1:main&Itemid=5 Your tool provider won’t tell you that, nor will those fancy methodology books, but verification is not all about mastering technical skills. True, those will help you very much in your daily work but verification is first and foremost TEAM WORK. But not only that, there are several key factors, or qualities if you will, that really distinguish the great verification teams from the good ones. Here there are:

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admin@thinkverification.com (Administrator) frontpage Thu, 24 Dec 2009 17:10:32 +0000